It will be appreciated that the term “semiconductor wafer” as used in this disclosure is intended to imply wafers used in the manufacture of all types of semiconductor devices, including, but not limited to, memory devices, ASICS, liquid crystal panels, and photovoltaic devices.
Current trends in the processing of the semiconductor wafers means that overlay budgets shrink with shrinking ground rules, and manufacturing processes are becoming more aggressive. Non-limiting examples of such aggressive manufacturing processes include high aspect ratio etching or deposition of exotic materials on a surface of the semiconductor wafer. The non-uniformity of some manufacturing processes over the semiconductor wafer surface and a plurality of manufacturing process steps may result in non-uniform stress being applied to the semiconductor wafer. When the semiconductor wafer deforms from one manufacturing process step to a subsequent manufacturing process step, e.g. from one lower layer to a subsequent layer on top of the lower layer, patterns in the upper layer may become misaligned to patterns in the lower layer. For the error free functioning of a semiconductor the relative position of patterns on the different layers to each is relevant. These relative positional errors are termed “overlay errors”. The need for smaller and denser structures on the semiconductor wafer means that an allowable tolerance for the overlay errors decreases.
The overlay error is determined by means of so-called “overlay marks”. In a lower layer together with the pattern for the semiconductor structure of the process step a first overlay mark is exposed in a photoresist film. After developing and processing this lower layer, the first overlay mark becomes part of the structure of this lower layer. On a higher layer in a subsequent process step together with the pattern for the semiconductor structure of the higher layer, a second overlay mark is exposed in a photoresist film. After development of the photoresist film the relative position error between the first overlay mark on the lower layer and the second overlay mark on the top layer can be measured in an overlay measurement tool. If the tolerance of the overlay error is too large the semiconductor wafer may be reworked with applied corrections. The goal is to use the measured overlay errors to compensate for the overlay errors in a next lot of semiconductor wafers, so as to minimize the overlay errors in the next lot and thus avoid costly rework.
From U.S. Patent Application Publication No. 2010/0030360 a method of calculating “alignment” residuals in a fabrication unit is known that comprises providing an alignment model including alignment model parameters; providing an exposure tool suitable for exposing a lot of semiconductor wafers in a plurality of exposure fields; retrieving alignment data comprising alignment values, measured by the exposure tool on the semiconductor wafers of the lot at a plurality of positions of the exposure fields that are used to calculate values for the alignment model parameters of the alignment model; calculating a set of alignment residuals from the alignment data by subtracting effects of the alignment model parameters for each of the plurality of measured positions and for each of the semiconductor wafer in the lot; and issuing a warning signal based upon a comparison between the set of alignment residuals and a set of reference values. The U.S. '360 document further comprises a system for calculating alignment residuals and a computer readable medium including instructions capable of performing the steps of calculating alignment residuals on a computer.
Ideally overlay measurements should be taken for each one of the semiconductor wafers at multiple positions on each exposure field on each of the semiconductor wafers to achieve a degree of precision and thus to achieve high yield rates for the fabrication of the semiconductor wafers. However, complete overlay measurements are very slow to perform, so they may cause a tool capacity problem. In other words, the time taken to perform a complete overlay measurement is a multiple of the time taken to process the semiconductor wafer. Thus, in order to provide the overlay measurements of each of the semiconductor wafers, a number of overlay measurement units has to be provided to distribute the overlay measurements on several parallel organised overlay measurement units.
The overlay measurement units are a significant cost factor in a semiconductor manufacturing process and for cost reasons the deployment of the parallel arranged overlay measurements units is avoided. Another solution for reducing limitations in the semiconductor manufacturing process whilst not extending the number of the overlay measurement units is to measure the overlay measurements in only a subset of the semiconductor wafers.
A reduction in the number of overlay measurements will increase the throughput of the semiconductor process. However, there will be a resultant reduction in the accuracy of the measurements and thus a reduction in the reliability of any values calculated from an interpolation of the measurements. This will not be serious if the absolute value of the overlay measurements only varies a little across the surface of the wafer. This assumption is not always valid.
Currently the only way of verifying the assumption is to carry out experiments which involve time and reduce the throughput of the semiconductor process.